Gaseous display driver circuits

ABSTRACT

Integrable driver circuits employing transistor-diode circuitry couple high voltage, alternating polarity sustaining signals to a plasma display while isolating the row and column selection pulses used for writing and erasing purposes. In one driver circuit arrangement, a charge storage diode is employed as a selection device and is connected in a &#39;&#39;&#39;&#39;Y&#39;&#39;&#39;&#39; with a pair of oppositely-poled switching diodes for coupling the sustaining signals. In another driver circuit arrangement, a single charge storage diode is employed for coupling both polarities of the sustaining signals.

United States Patent Dick 1 Sept. 5, 1972 [54] GASEOUS DISPLAY DRIVER CIRCUITS [72] George Wilmer Dick, Colts Neck,

Assignee: Bell Telephone Laboratories Incorporated, Murray Hill, NJ.

Filed: Dec. 16, 1970 Appl. No.: 98,754

Inventor:

52 us. 01 ..340/324 R, 307/281, 307/319, 315/169 R, 315/171, 340/166 EL, 340/173 1 cm .g0s1 s /315 01 022313 1334913afafi mas, 3 PL; 315/169 R, 171; 307/281, 319

References Cited UNITED STATES PATENTS CONTROL CCT.

SUSTAINING SIGNAL SOURCE WRITE ER/-\SE CIRCUITRY 8/ 1961 Livingston ..315/1 69 R 'WRITE- ERASE CIRCUITRY 403 COLUMN COLUMN 1 1971 Bitzeretal ....340/1731 L 3 ,500,075 3/1970 Hwang ..307/319 3,538,380 11/1970 Babb ..315/169 R 3,573,542 4/ 1971 Mayer et a1. ..340/324 R 3,590,315 6/1971 Hoff ..3l5/169 R Primary ExaminerDavid L. Trafton Attorney-R. J. Guenther and Kenneth B.- Hamlin '[57] ABSTRACT Integrable drivercircuits employing transistor-diode circuitry couple high voltage, alternating polarity sustaining signals to a plasma display while isolating the row and column selection pulses'used for writing nTnt, a charge storage diode is employed as a selection device and is connected in a Y with a pairv of oppositely-poled switching diodes for coupling the fi jr i mymg e ,31039119,Quv rcir u tatransfiv sustaining signals In another-driver circuit arrangement, a single charge storage diode is employed for coupling both polan'ties of the sustaining signals.

8 Claims, 3 Drawing Figures COLUMN DRIVER DRIVER DRIVER mtminssr 5 m2 3.689.912

SHEET 1 OF 2 FIG. CONTROL CCT. a:

VI WRITE-ERASE CIRCUITRY SUSTAINING SIGNAL j SOURCE \go T J v2 7 v3 v4 ICOLUMN COLUMN COLUMN DRIVER DRIVER. DRIVER C1: D (.J E Q x2 L|J (I) (I LIJ )1 g J 5 1".- g 30 Q Row J K50 x4 DRIVER F/GZ R OFF R= ON Y I*OFF +1 v RITE ERASE DISPLAY g m Q PULSE CELL O IIJ DRIVE- SIGNALS V I lNl/ENTOR G. W DICK gmv I 4/" OR-Mi) GASEOUS DISPLAY DRIVER CIRCUITS CROSS-REFERENCE TO RELATED APPLICATION BACKGROUND OF THE INVENTION This invention relates to matrix addressed systems and, more particularly, to driver circuitry for matrix addressed gaseous display systems.

Matrix addressed systems are typically employed to reduce the driver circuitry required and thereby reduce the size and cost of the overall system. Such systems are commonly employed in memories and displays, for example, row and column conductors thereof being arranged usually in a coordinate array of crosspoint memory or display cells. A particular crosspoint cell is selected by coincident drive signals applied to the individual row and column conductors defining the crosspoint.

Although matrix addressed systems reduce the driver circuitry required, the cost thereof is still relatively high in many applications at present, such as in systems requiring high crosspoint voltage or current levels or requiring alternating polarity drive signals. The problem is particularly acute in high voltage displays of the type generating display images through the lightemitting breakdown of a gaseous display material utilizing alternating polarity pulsed discharges, generally referred to as plasma displays. The usual driver circuitry employed with plasma displays includes pulse transformers, such as shown in D. Ngo application, Serial No. 821,410, filed May 2, 1969, which in the present state of the art cannot be fabricated in integrated circuit form.

memory which operates, in conjunction with alternating polarity sustaining polarity sustaining signals, to maintain selected cells lighted after application of write signals thereto. In accordance with my invention, the opposite polarity sustaining signals are provided by respective positive and negative sources coupled to the crosspoint display cells via oppositely-poled asymmetrical conduction devices connected to each row and column conductor. Thus, the driver circuitry associated with each row and column conductor, according to a feature of my invention, comprises a simple I Y-connected arrangement of a pair of oppositely- It is known inthe art to further reduce the driver cirv cuitry required, by employing tandem access matrices in which a pair of primary matrices are used to select row and column conductors" of a larger secondary matrix. However, tandem matrix arrangements often necessitate some form of coupling circuitry which mitigates their advantages somewhat, particularly in the case of transformer or amplifier coupling between the matrices.

SUMMARY OF THE INVENTION It is accordingly an object of this invention to reduce the size and cost of driver circuitry for matrix addressed systems, particularly ;for high voltage gaseous display systems.

It is another object of this invention to provide driver circuitry for plasma displays which is amenable to integrated circuit fabrication.

The above and other objects of my invention are attained in a simple and economical manner in several illustrative embodiments of a plasma display system employing transformerless, semiconductor driver circuitry. Plasma displays are characterized typically by gaseous display material disposed between first and second layers of dielectric material backed by mutually orthogonal row and column conductor arrays, thereby defining a coordinate array of crosspoint display cells. The capacitance provided by the dielectric material between the row and column conductor arrays provides each crosspoint display cell with inherent poled diodes and a selection device.

According to another aspect of my invention, a I

charge storage diode is employed as, the selection device for each row and column conductor. A particular row'or column conductor is selected by first charging the charge storage diode connected thereto and by thereafter applying a write or erase drivesignal in common-to all selection devices, such that only the single charged diode "passes the signal. A particular advantage of this two-phase operation using charge storage diode selection devices is that low level circuitry may be used for addressing and charging the selection devices, with one or two transistors employed in common for generating all the high voltage write and erase drive signals for the display.

- Still another feature of my invention relates to the use of a single charge storage diode in each driver circuit for coupling the alternating polarity sustaining signals to the row and column conductors of a plasma display. One polarity of the sustaining signals is coupled through the diode in the forward direction, storing charge in the diode to provide for coupling the opposite polarity sustaining signals therethrough.

I BRIEF DESCRIPTION OF THE DRAWING The above and other objects and features of the invention may be fully apprehended from the following detailed description and the accompanying drawing in which:

FIG. 1 is a diagram of an illustrative embodiment of a plasma display employing driver circuitry in accordance with the principles of my invention;

FIG. 2 is a time chart useful in describing the operation of the illustrative embodiment of FIG. 1; and

FIG. 3 is another illustrative embodiment of driver circuitry according to the principles of my invention DETAILED DESCRIPTION In FIG. 1 of the drawing an illustrative embodiment of driver circuitry is shown for driving plasma display 50. Plasma display 50 is depicted as having a coordinate array of crosspoint display cells defined by row conductors R1 through R4 and column conductors C1 through C4 disposed on respective dielectric material substrates. The dielectric material substrates are spaced apart and gaseous display material is-disposed therebetween.

As is well known in the art, plasma displays utilize the mechanism of electrical discharge breakdown of the gaseous display material at selected crosspoint display cells for generating images. When an electric field is applied across a display cell of a breakdown magnitude V determined by the pressure-distance characteristic of the particular gaseous display material employed, the gas in the crosspoint region breaks down and provides a light-emitting discharge of low current density. As the breakdown discharge and the resultant current flow are established initially at a crosspoint display cell, charge is stored on the dielectric material surfaces of the display cell in the immediate vicinity of the crosspoint. The stored charge opposes the voltage drop across the display cell and quickly reaches a level where the voltage across the cell becomes too low to maintain the discharge, thereby quenching the discharge at'the crosspoint. The stored charge provides the display cell with memory.

In operation, an alternating polarity sustaining signal provided by source 20 is extended by control circuit 80 across each display cell via the row and column drivers. Substantially one-half of the sustaining signal is provided on lead 21 to row drivers 30 and the other half is provided, of opposite polarity, on lead 22 to column drivers 40. The sustaining signal thus extended from source 20 across each display cell is of a magnitude less than the breakdown voltage level V}, and, for example, may be on the order of one-half the breakdown voltage level as depicted in FIG. 2. I

Addressing of the individual crosspoint display cells is effected using conventional addressing or scanning techniques, such as those 'known in the display and television art. The addressed cells are selectively energized or deenergized to write or erase information, respectively, in accordance with input signals received by writeserase circuitry 81 and 82from control circuit 80. An addressed display cell is turned ON or energized, for example, by a write pulse in the form of coincident signals applied to the particular row and column conductors defining the cell. The write pulse is of a magnitude sufficient to effect momentary breakdown of the gaseous display material at the addressed cell, permitting current flow thereacross to store charge on the adjacent dielectric material surfaces. The level of charge stored is determined principally by the net voltage across the cell during breakdown and, for the illustrative embodiment herein, is on the order of one-half the breakdown voltage level. During succeeding halfcycles of the sustaining signal, the charge stored on the dielectric material surfaces of the display cells, in combination with the sustaining signal voltage thereacross,

causes periodic breakdown of the gas at the display cells to emit light in the form of pulsed discharges. Conversely conversely, an addressed display cell is turned OFF by applying an erase pulse to the row and column conductor defining the cell, such that the erase pulse removes or erases the charge stored at the cell. The erase pulse is of sufficient magnitude, in combination with the stored charge, to cause momentary breakdown of the gas at the addressed display cell as depicted in FIG. 2. The resulting current flow removes the charge stored on the dielectric material surfaces of the cell, and no further discharge occurs at the cell until another write pulse is applied.

As mentioned above, the usual row and column driver circuitry employed with plasma displays includes pulse transformers for coupling the high voltage, alternating polarity sustaining signals to the display while isolating the row and column selection pulses used for writing and erasing. According to the present invention, the pulse transformers are eliminated by row and column drivers comprising compact and inexpensive arrangements suitable for integrated circuit fabrication. Specifically, in FIG. 1 each row driver 30 comprises charge storage diode 301, transistor selection switch 302 and load resistor 303. Similarly, each column driver 40 comprises charge storage diode 401, transistor selection switch 402 and load resistor 403.

It is assumed, as depicted in FIG. 2,.that display 50 is driven symmetrically about zero volts. Thus, row drivers 30 and column driver 40 are substantially identical in structure and operation, except that the polarities thereof are reversed, and the details of only one driver need be described. Consider then the operation of row driver 30 connected to row conductor R1, by way of example. When the positive polarity portion of the sustaining signal (herein referred to as the positive sustaining signal) is extended from source 20 over path 21, charge storage diode 301 couples it therethrough, the potential developed thereby across load resistor 303 being applied to row conductor R1. During this forward conduction period, a quantity. of charge is stored in diode 301 determined principally by the positive sustaining signal magnitude, load resistor 303 and the minority carrier lifetime of diode 301.

Consequently, during the immediately following negative polarity portion of the sustaining signal from sources 20 (herein referred to as the negative sustaining signal), diode 301 temporarily presents a low impedance until the stored charge is depleted. Upon depletion of the stored charge, diode 301 returns to its high impedance, reverse-biased state. Charge storage diode 301 remains in its high impedance state, permitting isolated application of write or erase pulses to selected conductors, until the next cycle of positive and negative sustaining signals. Thus, charge storage diode 301 provides a low impedance path for the positive and negative sustaining signals and presents a high impedance to the write and erase pulses.

The actual duration'of the negative sustaining signal applied to row conductor R1 by driver 30 is determined by the charge stored in diode 301 during conduction of the positive sustaining signal. Therefore, advantageously, the minority carrier lifetime of diode 301 is such that the duration of the negative sustaining signal determined thereby is substantially equal to the duration of the positive sustaining signal. Alternatively, however, two different load resistances may be employed for the positive and negative sustaining signals, respectively, rather than common load resistor 303, with the relative values of the two load resistors being chosen so as to produce substantially symmetrical sustaining signals. The respective sustaining signals may be steered to the appropriate load resistances by a diode connected in series with one sustaining signal load resistor and poled in the same direction as charge storage diode 301.

A particular display conductor, such as row conductor R1, is selected or addressed via an appropriate signal applied over lead X1 from write-erase circuitry 82 to the base of transistor selection switch 302. Switch 302 is thereby switched momentarily from its normally nonconducting state to a saturated, conducting state, connecting source 305 through to row conductor R1. Source 305 is connected to conductor R1 for different durations, depending upon whether write or erase operation is desired, the duration being controlled by the signal on lead X1.

In accordance with another aspect of my invention,

1 the alternating polarity sustaining signals may be provided advantageously by respective positive and negative sources coupled to the display through driver circuitry comprising a pair of oppositely-poled, fast switching diodes in place of charge storage diode 301 and load resistor 303. This aspect of the invention is described in detail below in connection with the embodiment of FIG. 3. However, briefly with reference to row driver 30 in FIG. 1, charge storage diode 301 and load resistor 303 may be replaced by a pair of diodes connected to row conductor R1 and poled opposite to one another. One diode of the pair connects the positive sustaining signals to row conductor R1 and the other diode connects the negative sustaining signals thereto. Thus, driver circuit 30 would comprise a simple Y-connect arrangement of the pair of diodes and selection switch 302 connected to row conductor R1. In FIG. 1, the driver transistors, such as transistors 302 and 402, are employed on a per row and per column basis to provide the logic-level to display-level voltage gains, in addition to the selection switch function. The number of drive transistors required can be reduced, substantially in many applications by arranging the row drivers and the column drivers in respective selection matrices, permitting the use of passive selection devices. For example, the row drivers for an illustrative 128 row display may be arranged in an 8 X16 selection matrix using 24 drive transistors instead of the 128 transistors according to the arrangement of FIG. 1. An alternative embodiment of driver circuitry arranged in a selection matrix is shown in FIG. 3 utilizing the above-mentioned Y-connect diode driver arrangement.

Row selection matrix 700 in FIG. 3 comprises a coordinate array of driver circuits 300 which correspond generally to row drivers 30 in FIG. 1. Sustaining signal source 200 in FIG. 3 corresponds generally to source 20 in FIG. 1 and includes positive and negative sources, as shown, for providing the corresponding positive and negative sustaining signals on respective leads. Thus, the positive. sustaining signals are provided over lead 210 to driver circuits 300 and the negative sustaining signals are provided over lead 211. Similarly, positive and negative sustaining signals are provided over respective leads 220 and 221 to column driver circuits (not shown) which are assumed to be arranged in a column selection matrix similar to row selection matrix 700.

Each driver circuit 300 comprises a selection device 312 and a pair of oppositely poled diodes 310 and 311 connected to a corresponding one of row conductors R1 through R4. The positive sustaining signals provided over lead 210 through diodes 361 are extended to the individual row conductors R1 through R4 via diodes 310 in the respective driver circuits 300. Similarly, the negative sustaining signals provided over lead 211 through diodes 351 are extended to the individual row conductors via diodes 311 in driver circuits 300. 300.

Selection device 312 in driver circuits 300 is depicted, according to a further aspect of the invention, as a charge storage diode in the illustrative embodiment of FIG. 3. However, it will be appreciated that other known selection matrix devices may be employed in driver circuits 300. Charge storage diode selection device 312 is normally reverse-biased in the absence of addressing signals from write-erase circuitry 820. The reverse biasing path for charge storage diode 312 connected to row conductor R1, for example, may be traced from source 342 through resistor 343, charge storage diode 312 and diode 311 in driver circuit 300, through diode 351 and resistor 355 to ground.

Writing and erasing are two-phase operations using the charge storage diode selection devices in the arrangement of FIG. 3. In the first phase, the particular driver circuit 300 is addressed for a selected row conductor and charge is stored in the charge storage diode in that driver circuit. For example, if a write or erase pulse is to be applied to row conductor R1, write-erase circuitry 820, under control of control circuit 80, provides selection matrix addressing signals on matrix addressing leads RXl and RYl. The addressing signals are such that current flows in the forward conduction direction through diode 312, the path thus being traced over lead RYl through diode 371, diode 310, charge storage diode 312 and diode 365 to lead RXl.

During the immediately following second phase of the operation, write-erase pulse generator 500 provides a write or erase pulse on lead 555 to each of driver circuits 300. The pulse is in a direction, illustratively positive-going in FIG. 3, such as to reverse bias the charge storage diodes in each of the driver circuits. However, the charge storage diode 312 in the single'driver circuit 300 addressed during the first phase of operation is forward biased by the charge stored therein, thereby extending the write or erase'pulse through to selected row conductor R1. Any charge remaining in charge storage diode 312 after passage of the write-erase pulse therethrough essentially decays by normal recombination before the next write-erase cycle. Removal of any remaining charge is also assisted by the succeeding negative sustaining signal. Alternatively, if desired in a particular application requiring faster charge depletion, a switched recovery circuit, such as a switched clamp which shunts resistor 355, may be employed advantageously.

A particular advantage of this two-phase operation using charge storage diode selection devices is that low level circuitry may be used for addressing and charging the selection devices, with write-erase pulse generator 500 employed in common for generating all the high voltage write and erase drive pulses for the row conductors of the display. It will be appreciated, of course, that the low-level write-erase circuitry should be isolatedfrom the high-voltage write-erase pulses and sustaining signals, such as by open-circuiting the matrix addressing leads during the intervals in which the high voltage signals are provided.

It is to be understood that the above-described arrangements are but illustrative of the application of the principles of my invention. Numerous other arrangements may be devised by those skilled in the art without departing from the spirit and scope of the invention.

What is claimed is:

1. In a matrix addressed system including an array of crosspoint cells defined by respective row and column conductors, a source of alternating polarity sustaining signals, and individual driver circuits respectively connected to each of said conductors for coupling said sustaining signals to said crosspoint cells in common and for selectively addressing individual ones of said cells; each of said driver circuits comprising a selection device adapted for selectively addressing a respective one of said conductors, and diode meansconnected between said source of sustaining signals and said respective one ofsaid conductors for continuously coupling said sustaining signals thereto.

means for applying "addressing signals in common to each of said driver circuits, and means for storing charge in said charge storage diode in a selected one of said driver circuits, thereby providing a low impedance 2. In a matrix addressed system including an array of crosspoint cells defined by respective row and column conductors, a source of alternating polarity sustaining signals, and individual driver circuits respectively connected to each of said conductors for coupling said sustaining signals to said crosspoint cells in common and for selectively addressing individual ones of said cells; each of said driver circuits comprising a selection device adapted for selectively addressing a respective one of said conductors, and diode means connected between said source of sustaining signals and said respective one of said conductors for couplingsaid sustaining signals thereto, said diode means comprising a charge storage diode poled so as to store charge during conduction of one polarity of said sustaining signals, said stored charge providing for conduction-of the other polarity of said sustaining signals through said diode.

3. In a matrix addressed system including an array of crosspoint cells defined by respective row and column.

conductors,'a source of alternating polarity sustaining signals, and individual driver circuits respectively connected to each of said conductors for coupling said sustaining signals to said crosspoint cells in common and for selectively addressing individual ones of said cells; each of said driver circuits comprising a selection device adapted for selectively addressing a respective one of said conductors, and diode means connected between said source of sustaining signals and said respective one of said conductors for coupling said sustaining signals thereto; said source of sustaining signals comprising a source of positive polarity sustaining signals and a source of negative polarity sustaining signals, and said diode means comprising a pair of oppositely poled diodes, one of said diodes coupling the positive polarity sustaining signals and the other of said diodes coupling the negative polarity sustaining signals to said respective one of said conductors.

4. A system according to claim 3 wherein said selection device comprises a charge storage diode adapted to provide a normally high impedance path to signals for addressing said respective one of said conductors.

5. A system according to claim 4 further comprising path for said addressing signals through said selected one driver circuit.

6. A pulsed discharge gaseous display system including an array of display cells defined by respective pairs of conductors; a s urce of posi ive and negative olarity sustaining sign 5; a source 0 write-erase sign s; and

individual driver circuits respectively connected to each of said conductors; said driver circuits each comprising a pair of oppositely poled diodes for respectively coupling said positive and negative polarity sustaining signals to a respective one of said conductors, and an asymmetrically conducting selection device connected between said source of write-erase signals and said respective one conductor, said selection device storing an electrical charge when a corresponding one of said display cells is addressed, thereby coupling said write-erase signals to said respective one conductor.

7. Adriver circuit for use ha plasma display, said driver circuit comprising three input terminals, an output terminal, and a pair of oppositely poled diodes and a charge storage diode respectively connecting said three input terminals in common to said output terminals, said pair of diodes adapted for respectively coupling positive and negative sustaining signals to the display, and said charge storage diode adapted when charge is stored therein to provide a low impedance path for coupling write-erase signals to the display.

8. A matrix array of driver circuits for coupling alternating polarity-signals in common to respective ones of a plurality of drive conductors and for coupling addressing signals selectively to said respective ones of said drive conductors; said array comprising a first set of matrix leads for connecting one polarity of said alternating polarity signals to said driver circuits; a second set of matrix leads for connecting the other polarity of said alternating polarity signals to said driver circuits; a third set of matrix leads for connecting said addressing signals to said driver circuits; and a fourth set of leads individually connecting said drive conductors to respective ones of said driver circuits; each of said driver circuits including a first diode connected between one of said first set and one of said fourth set of leads, a second diode connected between one of said second set and one of said fourth set of leads, and a third diode having a long minority carrier lifetime connected between one of said third set and one of said fourth set of leads, said first diode poled for conduction of said one polarity signals, said second diode poled for conduction of said other polarity signals, and said third diode poled against conduction of said addressing signals, said third diode conducting said addressing signals substantially only when charge is stored therein. 

1. In a matrix addressed system including an array of crosspoint cells defined by respective row and column conductors, a source of alternating polarity sustaining signals, and individual driver circuits respectively connected to each of said conductors for coupling said sustaining signals to said crosspoint cells in common and for selectively addressing individual ones of said cells; each of said driver circuits comprising a selection device adapted for selectively addressing a respective one of said conductors, and diode means connected between said source of sustaining signals and said respective one of said conductors for continuously coupling said sustaining signals thereto.
 2. In a matrix addressed system including an array of crosspoint cells defined by respective row and column conductors, a source of alternating polarity sustaining signals, and individual driver circuits respectively connected to each of said conductors for coupling said sustaining signals to said crosspoint cells in common and for selectively addressing individual ones of said cells; each of said driver circuits comprising a selection device adapted for selectively addressing a respective one of said conductors, and diode means connected between said source of sustaining signals and said respective one of said conductors for coupling said sustaining signals thereto, said diode means comprising a charge storage diode poled so as to store charge during conduction of one polarity of said sustaining signals, said stored charge providing for conduction of the other polarity of said sustaining signals through said diode.
 3. In a matrix addressed system including an array of crosspoint cells defined by respective row and column conductors, a source of alternating polarity sustaining signals, and individual driver circuits respectively connected to each of said conductors for coupling said sustaining signals to said crosspoint cells in common and for selectively addressing individual ones of said cells; each of said driver circuits comprising a selection device adapted for selectively addressing a respective one of said conductors, and diode means connected between said source of sustaining signals and said respective one of said conductors for coupling said sustaining signals thereto; said source of sustaining signals comprising a source of positive polarity sustaining signals and a source of negative polarity sustaining signals, and said diode means comprising a pair of oppositely poled diodes, one of said diodes coupling the positive polarity sustaining signals and the other of said diodes coupling the negative polarity sustaining signals to said respective one of said conductors.
 4. A system according to claim 3 wherein said selection device comprises a charge storage diode adapted to provide a normaLly high impedance path to signals for addressing said respective one of said conductors.
 5. A system according to claim 4 further comprising means for applying addressing signals in common to each of said driver circuits, and means for storing charge in said charge storage diode in a selected one of said driver circuits, thereby providing a low impedance path for said addressing signals through said selected one driver circuit.
 6. A pulsed discharge gaseous display system including an array of display cells defined by respective pairs of conductors; a source of positive and negative polarity sustaining signals; a source of write-erase signals; and individual driver circuits respectively connected to each of said conductors; said driver circuits each comprising a pair of oppositely poled diodes for respectively coupling said positive and negative polarity sustaining signals to a respective one of said conductors, and an asymmetrically conducting selection device connected between said source of write-erase signals and said respective one conductor, said selection device storing an electrical charge when a corresponding one of said display cells is addressed, thereby coupling said write-erase signals to said respective one conductor.
 7. A driver circuit for use in a plasma display, said driver circuit comprising three input terminals, an output terminal, and a pair of oppositely poled diodes and a charge storage diode respectively connecting said three input terminals in common to said output terminals, said pair of diodes adapted for respectively coupling positive and negative sustaining signals to the display, and said charge storage diode adapted when charge is stored therein to provide a low impedance path for coupling write-erase signals to the display.
 8. A matrix array of driver circuits for coupling alternating polarity signals in common to respective ones of a plurality of drive conductors and for coupling addressing signals selectively to said respective ones of said drive conductors; said array comprising a first set of matrix leads for connecting one polarity of said alternating polarity signals to said driver circuits; a second set of matrix leads for connecting the other polarity of said alternating polarity signals to said driver circuits; a third set of matrix leads for connecting said addressing signals to said driver circuits; and a fourth set of leads individually connecting said drive conductors to respective ones of said driver circuits; each of said driver circuits including a first diode connected between one of said first set and one of said fourth set of leads, a second diode connected between one of said second set and one of said fourth set of leads, and a third diode having a long minority carrier lifetime connected between one of said third set and one of said fourth set of leads, said first diode poled for conduction of said one polarity signals, said second diode poled for conduction of said other polarity signals, and said third diode poled against conduction of said addressing signals, said third diode conducting said addressing signals substantially only when charge is stored therein. 